The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device. The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), EEPROM (electrically erasable programmable read only memory), EEPROM-EAROMs and non-volatile SRAMs. Different types of devices have been developed for specific applications requirements in each of these segments. These parts have been developed with a focus on the high endurance and high speed requirements.
The basic technologies used to manufacture electrically programmable ROMs all utilize to some extent Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-silicon dioxide interface and into the oxide conduction band. The thin silicon dioxide layer allows charges to tunnel through when a voltage is applied to the gate. These charges are trapped in the silicon dioxide to silicon nitride interface and remain trapped there since the materials are high quality insulators.
Take the EEPROM as an example, in programming mode, a negative voltage is applied to the source and drain while the substrate and gate are grounded. The potential at the central portion of the channel became almost the same as that of the drain and source so that tunneling electrons move from the silicon to the nitride through the thin oxide layer and the electrons are trapped in the nitride. In the mode of erasing, electrons are emitted from the traps in the nitride by applying a negative voltage to the gate electrode while the source and the drain are grounded.
Various nonvolatile memories have been disclosed in the prior art. For example, Mitchellx has proposed EPROMs with self-aligned planar array cell. In this technique, buried diffusion self-aligned to the floating gate avalanche injection MOS transistor are used for the bit lines. Cross point array technology has been disclosed. The self-aligned source and drain will allow this device to be optimized even further for programming speed. See "A New Self-Aligned Planar Cell for Ultra High Density EPROMs, A. T. Mitchellx, IEDM, Tech. pp. 548-553, 1987". Bergemont proposed another cell array for high density flash EEPROM, which can be seen in "NOR Virtual Ground (NVG)- A New Scaling Concept for Very High Density FLASH EEPROM and its Implemntation in a 0.5 .mu.m Process, A Bergemont, IEEE, pp. 15-18, 1993". This cell structure is introduced for scaling down the size of the devices to fabricate high density EEPROMs. In the flash array schematic, one metal bit line is shared between two columns of cells. The NVG array uses select devices at the top and bottom of each array block. The metal bit lines are connected through contacts to every other diffusion bit line. Another prior art that relates to the field is the article "A 0.67 um2 Self-Aligned Shallow Trench Isolation Cell (SA-STI CELL) for 3V-only 256 Mbit EEPROMs, S. Aritome, IEEE, pp. 61-64, 1994". Aritome proposed a NAND structure EEPROM that reduces the cell size without scaling of the device dimension.
Typically, the high density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Further, it can be used to replace magnetic disk memory. However, it is difficult to make the sub-0.1 .mu.m nonvolatile memory by using the current lithography technology.